Acebron Anton, José Jesús

1. José Jesús Acebron Anton. Sistemas distribuidos de gestión de documentos multimedia. Universitat Politècnica de Catalunya. 10-1997

Acosta Elias, Jesús

1. Jesús Acosta-Elias, Leandro Navarro-Moldes. A Demand based Algorithm for Rapid Updating of Replicas. IEEE Workshop on Resource Sharing in Massively Distributed Systems, pg. . 7-2002
2. Jesús Acosta-Elias, Leandro Navarro-Moldes. Behaviour of the fast consistency algorithm in the set of replicas with multiple zones with high demand. Symposium on Informatics and Telecommunications, pg. . 9-2002
3. Jesús Acosta-Elias, Joan Manuel Marquès, Leandro Navarro. Generalization of The Fast Consistency Algorithm To a Grid With Multiple High Demand Zones. International Conference on Computational Science, pg. . 2-2003
4. Jesús Acosta Elias. Algoritmos de consistencia rápida orientados por la demanda en sistemas distribuídos de gran escala. Universitat Politècnica de Catalunya. 6-2003

Ardaiz , Oscar

1. O. Ardaiz, F. Freitag, L. Navarro. Improving the Service Time of Web Clients using Server Redirection. 2nd Workshop on Performance and Architecture of Web Servers, pg. . 6-2001
   • Tambe publicat a: ACM Sigmetrics Performance Evaluation Review, 29(2). .
2. O. Ardaiz, F. Freitag, L. Navarro. Multicast Injection for Application Network Deployment. Web Caching and Content Distribution, pg. Boston, USA. 6-2001 [wccd2001-oardaiz.pdf]
3. O. Ardaiz, F. Freitag, L. Navarro. On Service Deployment in Ubiquitous Computing. Ubiquitous Computing. Barcelona. 9-2001 [ucw2001-oardaiz.zip]
   • Conjuntament amb PACT
4. O. Ardaiz, F. Freitag, L. Navarro. Multicast Injection for Application Network Deployment. Local Computer Networks, pg. Tampa, USA. 11-2001 [lcn2001-oardaiz.pdf]
5. O. Ardaiz, L. Navarro. Xweb: A Framework for Application Network Deployment. Jornadas Telematica, pg. Gran Canaria, Spain. 9-2003 [jitel2003-oardaiz.pdf]
6. Oscar Ardaiz. Application Network Deployment in the Internet. Politecnica Catalunya. 1-2004 [phd2004-oardaiz.zip]
7. O. Ardaiz, L. Navarro. Xweb: A Framework for Application Network Deployment. Euromicro Conference in Paralel and Distributed Processing, pg. A Coruña. 2-2004 [pdp2004-oardaiz.pdf]

Barcelo Ordinas, Jose M.

1. M. Mitrou, V. Nellas, A. Martínez, L. Jaussi, J. M. Barceló. First Results and Analysis of Traffic Experiments performed by EXPLOIT WP3.2 on the ETB. 14th Exploit Traffic Workshop. Basel, Suiza. 09-1994
2. F. Cerdán, J. M. Barceló, J. García, O. Casals. Protocolo de control de Acceso al medio para una Red de acceso ATM. IV Jornadas TELECOM I+D, pg257-266. Madrid. 11-1994
3. J. M. Barceló, O. Casals, L. Jaussi, M. Mitrou, V. Nellas. Results on experiments on resource management on the ETB. ATM Hot Topics on Traffic and Performance: from RACE to ACTS. Milan. 06-1995
4. J. M. Barceló, J. García-Vidal, O. Casals. Comparison of models for the multiplexing of worst case traffic sources. WATM; First Workshop on ATM Traffic Management, pg41-48. Paris. 12-1995 [watm1995-joseb.ps]
5. J. García-Vidal, J. M. Barceló, O. Casals. An exact Model for the multiplexing of worst case traffic sources. IFIP Conference on Performance on Computer Networks (HPCN\'95), pg3-17. Instanbul, Turkey. 12-1995 [hpc1995-joseb.ps]
6. L.Jaussi, J.M. Barceló, S. Louis, O. Casals. Experimental Evaluation of CDV impact on ATM Resource Management. European Transactions on Telecommunications, Vol 7, Nº 5, pg407-422. AEI. 10-1996 [ett1996-joseb.ps]
7. F. Panken, J. M. Barceló, B. Miah, S. Winstanley. Investigations on delay and CDV in an ATM based optical Network. IEEE ATM\'97 Workshop. Lisboa. 05-1997 [atm-w1997-joseb.ps]
8. Jose Mª Barcelo Ordinas. Analytical Models for the Multiplexing of Worst Case Traffic Sources and their Application to ATM Traffic Control. UPC. 04-1998 [phd1998-joseb.pdf]
9. . M. Barceló, J. García-Vidal. Multiplexing periodic sources in a tree network. 4th International Conference on Broadband Communications, pg577-588. Sttutgart. 04-1998 [bc1998-joseb.ps]
10. José Mª Barceló, Jorge García-Vidal, Olga Casals. Worst Case Traffic in a Tree Network of ATM Multiplexers. IEEE/ACM Transactions on Networking, Vol 8, Nº 4, pg507 - 516. ACM Press New York, NY, USA. 08-2000 [ieee/acm ton2000-joseb.pdf]

Borensztejn , Patricia

1. Patricia Borensztejn, Jesús Labarta and Cristina Barrado. Measures of Parallelism at Compile Time. Euromicro Workshop on Parallel and Distributed Processing, pg253-258. . 1-1993
2. Patricia Borensztejn, Jesús Labarta and Cristina Barrado. Measures of Parallelism (II). Sixth IASTED/ISMM Internacional Conference Parallel and Distributed Computing and Systems, pg63-67. . 10-1994
3. Patricia Borensztejn. Medidas de Paralelismo: Un Estudio sobre sus Límites en los Programas Reales. Universitat Politècnica de Catalunya. 12-1998
4. Patricia Borensztejn, Cristina Barrado and Jesús Labarta. Influence of Variable Time Operations in Static Instruction Scheduling. 5th International Euro-Par Conference , pg213-216. . 1-1999

Cerdà Alabern , Llorenç

1. Ll. Cerdà, J. García, O. Casals. A Study of the Fairness of the Fast Reservation Protocol. IFIP TC6 3th Workshop on Performance Modelling and Evaluation of ATM Networks, pg13. Bradford, UK. 7-1995 [perfatm1995-llorenc.ps]
2. Ll. Cerdà, O. Casals. Improvements and Performance Study of the Conformance Definition for the ABR Service in ATM Networks. ITC Specialists Seminar on Control in Communications, pg12. Lund, Sweden. 9-1996 [itcss1996-llorenc.ps]
3. Ll. Cerdà, O. Casals. Charging of the ABR Service in ATM Networks. 6th Open Workshop on High Speed Networks. Stuttgart, Germany. 10-1997 [whsn1997-llorenc.ps]
4. Ll. Cerdà, O. Casals. Effective Usage of the CCR in the ABR Service Management. International Conference for Computer Communications, pg7. Cannes, France. 11-1997 [iccc1997-llorenc.ps]
5. Llorenç Cerdà, Olga Casals. Charging of the ABR Service in ATM Networks: a Numerical Example . looking .forward - A supplement to Computer. The IEEE Computer Society\'s Student Newsletter, V. 6, N. 1, pg3. IEEE. 4-1998 [computer1998-llorenc.ps]
6. Llorenç Cerda and Olga Casals. Dynamic and Static Charging of the ABR Service in ATM Networks. GLOBECOM\'98, pg. . 11-1998
7. Llorenç Cerdà Alabern. Traffic Management of the ABR Service Category in ATM Networks. Universitat Politècnica de Catalunya. 10-1999 [phd1999-llorenc.pdf]
8. Ll. Cerdà, B. Van Houdt, O. Casals, C. Blondia. Performance Evaluation of the Conformance Definition for the ABR Service in ATM Networks. Broadband Communications\'99, pg13. Hong Kong. 11-1999 [bc1999-llorenc.ps]

Cerdán Cartagena, Fernando

1. Fernando Cerdán and Olga Casals. Peformance of Different TCP Implementations over the GFR Service Category. Interoperable Communication Networks , pg. . 1-2000
2. F. Cerdan. O. Casals. Mapping and Internet Assured Service on the GFR ATM Service. Networking 2000, pg. . 5-2000
3. Fernando Cerdán Cartagena. Solutions for Service Integration in ATM Networks. Universitat Politècnica de Catalunya. 10-2000

Corbal San Adrian , Jesus

1. J. Corbal, R. Espasa, M. Valero. Command Vector Memory Systems: High Performance at Low Cost. IX Jornadas de Paralelismo, pg299-306. . 9-1998
2. J. Corbal, R. Espasa, M. Valero. Command-Vector Memory System. Parallel Architectures and Compilation Techniques (PACT\\\'98), pg68-77. . 9-1998 [pact1998-jcorbal.ps]
3. Jesus Corbal, Roger Espasa and Mateo Valero . MOM: a Matrix SIMD Instruction Set Architecture for Multimedia Applications. Supercomputing 99 , pg. Portland. 11-1999 [sc1999-jcorbal.ps]
4. Jesus Corbal, Roger Espasa, Mateo Valero. Exploiting a New Level of DLP in Multimedia Applications. 32nd Annual IEEE/ACM International Symposium on Microarchitecture, pg72-79. Haifa, Israel. 11-1999 [micro1999-jcorbal.ps]
5. Jesus Corbal, Roger Espasa, Mateo Valero. DLP + TLP Processors for the Next Generation of Media Workloads. Seventh International Symposium on High-Performance Computer Architecture (HPCA\'01), , pg219-228. Monterrey, Mexico. 1-2001 [hpca2001-jcorbal.ps]
6. Jesus Corbal, Roger Espasa, Mateo Valero. On the Efficiency of Reductions in µ-SIMD Media Extensions. International Conference on Parallel Architectures and Compilation Techniques (PACT\'01) , pg83-95. Barcelona, Spain. 9-2001 [pact2001-jcorbal.ps]
7. Jesus Corbal San Adrian. N-dimensional vector ISAs for multimedia applications. Universitat Politècnica de Catalunya (UPC). 7-2002 [phd2002-jcorbal.ps]
8. Jesus Corbal, Roger Espasa, Mateo Valero. Three-dimensional memory vectorization for high bandwidth media memory systems. 35th Annual International Symposium on Microarchitecture (MICRO35), pg149-160. Estambul, Turkey. 9-2002 [micro2002-jcorbal.pdf]

Corbalan , Julita

1. Xavier Martorell, Julita Corbalán, Dimitrios Nikolopoulos , José I. Navarro , Eleftherios Polychronopoulos , Theodore Papatheodorou , Jesús Labarta. A Tool to Schedule Parallel Applications on Multiprocessors: the NANOS CPU Manager. Lecture Notes Computer Science , 1911, pg55-69. Springer-Verlag. 5-2000 [lncs2000-juli.ps]
2. Julita Corbalan, Xavier Martorell, Jesus Labarta. Performance-Driven Processor Allocation . Symposium on Operating Systems Design and Implementation, pg74-79. San Diego, EEUU. 10-2000 [osdi2000-juli.pdf]
3. Felix Freitag, Julita Corbalan, Jesus Labarta. A Dynamic Periodicity Detector: Application to sSpeedup Computation. International Parallel and Distributed Processing Symposium, pg2-7. San Francisco, EEUU. 4-2001 [ipdps2001-juli.pdf]
4. Julita Corbalám, Xavier Martorell, Jesús Labarta. Improving Gang Scheduling through Job Performance Análisis and Malleability. International Conference on Supercomputing, pg303-311. Sorrento. 6-2001 [ics2001-juli.pdf]
5. Julita Corbalán, Jesús Labarta. Improving Processor Allocation through Run-Time Measured Efficiency. International Parallel and Distributed Processing Symposium, pg74-79. San Francisco, EEUU. 4-2002 [ipdps2002-juli.pdf]
6. Julita Corbalan. Coordinated Scheduling and Dynamic Performance Análysis in Multiprocessor Systems . Universitat Politècnica de Catalunya. 7-2002 [phd2002-juli.pdf]
7. Julita Corbalán, Jesus Labarta, Xavier Martorell. Evaluation of the Memory Page Migration Influence in the System Performance: The case of the SGI O2000. International Conference on Supercomputing, pg121-129. San Francisco,EEUU. 6-2003 [ics2003-juli.pdf]

Cornetta, Gianluca

1. Gianluca Cornetta and Jordi Cortadella. A radix-16 SRT division unit with speculation of quotient digits. Great Lakes Symposium on VLSI, pg74-77. . 3-1999
2. Gianluca Cornetta and Jordi Cortadella. A multi-radix approach to asynchronous division. International Symposium on Advanced Research in Asynchronous Circuits and Systems, pg25-34. . 3-2001
3. Gianluca Cornetta. Design and Análisis of Variable-delay Arithmetic Units. Universitat Politècnica de Catalunya. 12-2001

Cortés Rosselló , Antonio

1. T. Cortes, S. Girona and J. Labarta. PACA: A Cooperative File-system Cache for Parallel Machines. 2nd International Euro-Par Conference , pg477--486. Lyon, frnace. 8-1996
   • Tambe publicat a: Lecture Notes in Computer Science, 1123. Spinger.
2. T. Cortes, S. Girona and J. Labarta. Avoiding the Cache-coherence Problem in Parallel/Distribute File Systems. High Performance Computing and Networking , pg860--869. Viena, Austria. 4-1997
   • Tambe publicat a: Lecture notes in Computer Science, 1225. Springer.
3. T. Cortes, S. Girona, J. Labarta. Design Issues of a Cooperative Cache with no Coherence Problems. 5th workshop on I/O in Parallel and Distributed Systems . San José, CA, EUA. 11-1997
4. Antonio Cortés Rosselló. Cooperative Caching and Prefetching in Parallel/Distribute File Systems. Universitat Politècnica de Catalunya. 12-1997
5. T. Cortes, J. Labarta. PAFS: a new Generation in Cooperative Caching. International Conference on Parallel and Distributed Processing Techniques and Applications, pg267--274. Las vegas, NV, EUA. 7-1998
6. T. Cortes, J. Labarta. Linear Aggressive Prefetching: A way to Increase the Performance of Cooperative Caches . International Parallel Processing Symposium, pg46--54. Puerto Rico. 4-1999

del Corral , Anna

1. A.M. del Corral y J.M. Llabería. Hardware Support to Reduce Conflicts between Vector Streams. 2nd International Workshop on Massive Parallelism: Hardware, Software and Applications, pg. Capri, Italy. 10-1994 [mp1994-anna.ps]
2. A.M. del Corral y J.M. Llabería. Out-of-Order Access to Vector Elements in Order to Reduce Conflicts in Vector Processors. Sixth IEEE Symposium on Parallel and Distributed Processing, pg. Dallas, USA. 10-1994 [spdp1994-anna.ps]
3. A.M. del Corral y J.M. Llabería. Access Order to Avoid Inter-Vector-Conflicts in Complex Memory Systems. 9th International Paralel Processing Symposium, pg. Santa Barbara, USA. 4-1995 [ipps1995-anna.ps]
4. A.M. del Corral y J.M. Llabería. Avoiding the Use of Buffers in Skewed Memory Systems for Vector Processors. High Performance Computing, pg. New Delhi, India. 12-1995 [hipc1995-anna.ps]
5. A.M. del Corral y J.M. Llabería. Reducing Inter-Vector-Conflicts in Complex Memory Systems. Int. Conference on Supercomputing, pg. Philadelphia, USA. 5-1996 [ics1996-anna.ps]
6. A.M. del Corral y J.M. Llabería. Increasing the Effective Memory Badwidth in Multivector Processors. EUROMICRO Conference, pg. Praga. 9-1996 [euromicro1996-anna.ps]
7. A.M. del Corral y J.M. Llabería. Increasing the Effective Badwidth of Complex Memory Systems in Multivector Processors. Supercomputing’96, pg. Pittsburgh, USA. 11-1996 [sc1996-anna.ps]
8. Anna del Corral. Incremento del Rendimiento del Sistema de Memoria en Procesadores Vectoriales. UPC. 10-1997
9. A.M. del Corral y J.M. Llabería. New Access Order to Reduce Inter-Vector-Conflicts. VECPAR’98, pg. Oporto, Portugal. 6-1998 [vecpar1998-anna.ps]
10. A.M. del Corral y J.M. Llabería. Minimizing Conflicts between Vector Streams in Interleaved Memory Systems. IEEE Transactions on Computers, , pg. . 4-1999 [tc1999-anna.ps]

Díaz de Cerio , Luis M.

1. Luis Díaz de Cerio, Miguel Valero-García and Antonio González. Efficient FFT on Torus Multicomputers: A Performance Study. 2nd Austrian-Hungarian Workshop on Transputer Applications, pg233-242. . 9-1994
2. Luis Díaz de Cerio, Miguel Valero-García and Antonio González. A Study of the Communication Cost of the FFT on Torus Multicomputers. IEEE First International Conference on Algorithms and Architectures for Parallel Processing , pg131-140. . 4-1995
3. Antonio González, Miguel Valero-García and Luis Díaz de Cerio. Executing Algorithms with Hypercube Topology on Torus Multicomputers. IEEE Transactions on Parallel and Distributed Systems, vol. 6, no. 8, pg803-814. . 8-1995
4. Luis Díaz de Cerio, Miguel Valero-García and Antonio González. Overlapping Communication and Computation in Hypercubes. Second International Euro-Par Conference , pg253-257. . 8-1996
   • Tambe publicat a: Lecture Notes in Computer Science , 1123. .
5. Luis Díaz de Cerio, Antonio González and Miguel Valero-García. Communication Pipelining in Hypercubes. Parallel Processing Letters, vol. 6, no. 4, pg507-523. . 12-1996
6. Luis Díaz de Cerio, Antonio González and Miguel Valero-García. A Method for Exploiting Communication/Computation Overlap in Hypercubes. Parallel Computing, vol. 24, no. 2, pg221-245. . 6-1998
7. Miguel Valero-García, Antonio González, Luis Díaz de Cerio and Dolors Royo. Divide-and-Conquer Algorithms on Two-Dimensional Meshes. 4th International Euro-Par Conference , pg1051-1056. . 9-1998
   • Tambe publicat a: Lectur Notes in Computer Science, 1470. .
8. Luis M. Díaz de Cerio. CALMANT: Un Metodo Sistemático para la Ejecución de Algoritmos con Topología Hipercubo en Multicomputadores. Universitat Politècnica de Catalunya. 12-1998
9. Luis Díaz de Cerio, Miguel Valero-García and Antonio González. Complete Exchange Algorithms for Meshes and Tori Using a Systematic Approach. 6th International Euro-Par Conference , pg591-594. . 8-2000
   • Tambe publicat a: Lecture Notes in Computer Science , 1900. .
10. Luis Díaz de Cerio, Miguel Valero-García, Antonio González and Dolors Royo. CALMANT: Un método Sistemático para la Ejecución de Algoritmos Hipercubo en Sistemas Multiprocesador. Computación y Sistemas, vol. 4, no. 4, pg289-297. . 4-2001
11. Luis Diaz de Cerio, Miguel Valero-Garcia, Antonio Gonzalez and Dolors Royo. CALMANT: A Systematic Method for the Execution of Hypercube Algorithms in Multiprocessor Systems. Computación y Sistemas, vol. 4, no. 4, pg298-305. . 4-2001
12. Luis Díaz de Cerio, Miguel Valero-García and Antonio González. Hypercube Algorithms on Mesh Connected Multicomputers. IEEE Transactions on Parallel and Distributed Systems, vol. 13, no. 12, pg1247-1260. IEEE. 12-2002

Fontdecaba Baig, Enric

1. Enric Fontdecaba, José M. Cela and Juan C. Dürsteler. Parallel Optimisation for Optical Lens Design. 3rd International Meeting on Vector and Parallel Processing (VECPAR\'98), pg657-662. . 6-1998
2. Enric Fontdecaba, José M. Cela and Juan C. Dürsteler. On the parallelisation of Non-Linear Optimisation Algorithms for Ophthalmical Lens Design. 4th International Workshop on Applied Parallel Computing in Large Scale Scientific and Industrial Problems (PARA\'98), pg1-7. . 6-1998
3. Enric Fontdecaba Baig. High Performance Algorithms for Progressive Addition Lens Design. Universitat Politècnica de Catalunya. 7-2000

Gallego Fernandez , Isabel

1. Delgado J., Gallego I. and Polo J. . Electronic Commerce of Multimedia Services. 7th International Conference on Multimedia Modelling , pg. Ottawa, Canada. 10-1999
2. Delgado, J. and Gallego I.. Evolution of Broker Agents in Electronic Commerce of Multimedia Products and Services. First Asia-Pacific Conference on Intelligent Agent Technology. Workshop on Agents in E-Commerce, pg. Hong Kong. 12-1999
3. Gallego I., Delgado J. and García R.. Use of Mobile Agents for IPR Management and Negotiation. 2th International Workshop on Mobile Agents for Telecommunication Applications , pg. Paris, France. 9-2000
4. Delgado J. and Gallego I. . Distributed Negotiation of Digital Rights. International Conference on Media Futures , pg. Florence, Italy. 5-2001
5. Isabel Gallego Fernandez. Modelos para Comercio Electrónico Basados en Sistemas Intermediarios. UPC. 7-2001
6. Delgado J. and Gallego I.. Negotiation of copyright in E-Commerce of multimedia publishing material. 5th International ICCC/IFIP Conference on Electronic Publishing , pg. Carterbury, UK. 7-2001
7. J. Delgado, I. Gallego, X. Perramon. Broker-based Secure Negotiation of Intellectual Property Rights. 4th International Information Security Conference, pg. . 10-2001

Girona Turell, Sergi

1. Sergi Girona, Santi Bello, Jesús Labarta, Pablo Ribes, Román Martín, José Soto and Gloria Laffitte. The Queue System within PHASE. 7th International Conference High-Performance Computing and Networking, pg1171-1174. . 4-1999
2. Sergi Girona and Jesús Labarta. Sensitivity of Performance Prediction of Message Passing Programs. International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA\'99), pg620-626. . 6-1999
3. Sergi Girona, Jesús Labarta and Rosa M. Badia. Validation of Dimemas communication model for MPI collective operations. 7th EuroPVM/MPI\'2000, pg27-38. . 9-2000
4. Sergi Girona and Jesús Labarta. Sensitivity of Performance Prediction of Message Passing Programs. Journal of Supercomputing, vol. 17, no. 3, pg291-298. . 11-2000
5. Toni Cortés, Sergi Girona and Jesús Labarta. Design Issues of a Cooperative Cache with no Coherence Problems. High Performance Mass Storage and Parallel I/O: Techniques and Applications, , pg. . 1-2002
6. Sergi Girona Turell. Performance Prediction and Evaluation Tools. Universitat Politècnica de Catalunya. 7-2003

Gonzalez Perez, M. Almudena

1. M. Almudena Gonzalez Perez. Modelos de Seguridad para Móviles. Universidad Politécnica de Cataluña. 7-2001

Gonzalez Sanchez, José Luis

1. José Luis González Sánchez, Jordi Domingo-Pascual. Revisión y clasificación de los protocolos para redes de tecnología ATM. Boletín RedIRIS, 46-47, pg64-74. . 1-1999
2. José Luis González-Sánchez, Jordi Domingo-Pascual. Protocols for ATM Networks: Survey, classification and new trends. Telecom I+D, pg. . 11-1999
3. José Luis González-Sánchez, Jordi Domingo-Pascual. TAP: Architecture for Trusted Transfers in ATM Networks with Active Switches. IEEE Conference on High Performance Switching and Routing, pg105-112. . 6-2000
4. José Luis González-Sánchez, Jordi Domingo-Pascual. RAP: Protocol for Reliable Transfers in ATM Networks with Active Switches. International Conference on Communications in Computing (CIC 2000), pg141-147. . 6-2000
5. José Luis González-Sánchez, Jordi Domingo-Pascual. Protocolo Activo para Transmisiones Garantizadas sobre una Arquitectura Distribuida y Multiagente en Redes ATM. Simposio Español de Informática Distribuida, pg465-474. . 9-2000
6. José Luis González-Sánchez, Jordi Domingo-Pascual. Trusted and Active Protocol over a Distributed Architecture in ATM Networks with Software Agents. Ninth International Conference on Computer Communications and Networks, pg484-490. . 10-2000
7. José Luis Gonzalez Sanchez. Protocolo activo para transmisiones garantizadas sobre una arquitectura distribuida y multiagente en redes atm. Universitat Politècnica de Catalunya. 7-2001
8. José Luis González-Sánchez, Jordi Domingo-Pascual. Conexiones Robustas para Flujos TCP sobre ATM Mediante un Protocolo Activo en una Arquitectura Multiagente. III Jornadas de Ingeniería Telemática (JITEL), pg355-362. . 9-2001
9. José Luis González-Sánchez, Jordi Domingo-Pascual, Alfonso Gazo-Cervero. Robust Connections for TCP Transfers Over ATM Through an Active Protocol in a Multiagent Architecture. 10th International Conference on Telecommunications (ICT’03), pg. . 2-2003

Gonzalez Tallada , Marc

1. E. Ayguadé, M. Gonzalez, J. Labarta, X. Martorell, N. Navarro, J. Oliver. NanosCompiler: A Research Infrastructure for OpenMP Extensions. 1st European Workshop on OpenMP . Lund (Sweden). 10-1999 [ewomp1999-marc.pdf]
2. M. Gonzalez, J. Oliver, X. Martorell, E. Ayguadé, J. Labarta and N. Navarro. OpenMP Extensions for Thread Groups and Their Run-time Support. 13th International Workshop on Languages and Compilers for Parallel Computing, pg317-331. New York (USA). 08-2000 [lcpc2000-marc.pdf]
3. M. Gonzalez, J. Oliver, X. Martorell, E. Ayguadé, J. Labarta and N. Navarro. : Precedence Relations in the OpenMP Programming Model. 2nd European Workshop on OpenMP. Edimburgh (UK). 09-2000 [ewomp2000-marc.pdf]
4. M. Gonzalez, E. Ayguadé, X. Martorell and J. Labarta. Defining and Supporting Pipelined Executions in OpenMP. 2nd International Workshop on OpenMP Applications and Tools. . 07-2001 [wompat2001-marc.pdf]
5. M. Gonzalez, E. Ayguadé, X. Martorell and J. Labarta.. Complex Pipelined Executions in OpenMP Parallel Applications. International Conference on Parallel Processing , pg295-302. VAlencia (Spain). 09-2001 [icpp2001-marc.pdf]
6. M. Gonzalez, E. Ayguadé, X. Martorell, J. Labarta and P.V. Luong. Dual-Level Parallelism Exploitation with OpenMP in Coastal Ocean Circulation Modeling. 2nd Workshop on OpenMP: Experiences and Implementations . Kyoto (Japan). 05-2002 [wompei2002-marc.pdf]
7. Marc Gonzalez, Eduard Ayguadé, Xavier Martorell and Jesús Labarta. Exploiting Pipelined Executions in OpenMP. 32nd Annual International Conference on Parallel Processing, pg153-160. Kaohsiung, Taiwan. 10-2003 [icpp2003-marc.pdf]
8. Marc Gonzalez Tallada. Multilevel Parallelism Exploitation in Shared Memory Multiprocessors. Universitat Politecnica de Catalunya (UPC). 12-2003

González González , Jose

1. José González and Antonio González. Speculative Execution via Address Prediction and Data Prefetching. International Conference on Supercomputing , pg196-203. . 7-1997
2. José González and Antonio González. Memory Address Prediction for Data Speculation. 3rd International Euro-Par Conference , pg1084-1091. . 8-1997
3. Antonio Gonzalez, Jose Gonzalez and Mateo Valero. Virtual-Physical Registers. 4th International Symposium on High-Performance Computer Architecture, pg175-184. . 1-1998
4. José González and Antonio González. Limits of Instruction Level Parallelism with Data Value Speculation. 3rd International Meeting on Vector and Parallel Processing , pg585-598. . 6-1998
5. José González and Antonio González. The Potential of Data Value Speculation to Boost ILP. International Conference on Supercomputing , pg21-28. . 7-1998
6. José González and Antonio González. Control-flow Speculation through Value Prediction for Superscalar Processors. 1999 International Conference on Parallel Architectures and Compilation Techniques , pg57-65. . 10-1999
7. Jose González González. Speculative Execution Through Value Prediction. Universitat Politècnica de Catalunya . 1-2000

Hundessa , Lemma

1. Lemma Hundessa, Jordi Domingo-Pascual. Fast rerouting mechanism for a protected label switched path. IEEE International Conference on Computer Communication and networks, pg527-530. Scottsdale, Arizona, USA. 10-2001 [icccn2001-hundessa.pdf]
2. Lemma Hundessa, Jordi Domingo-Pascual. A Reliable QoS Provision and Fast Recovey Method for Protected LSP in MPLS-Based Networks. IEEE International Conference on Networking , pg307-318. Atlanta, Georgia, USA.. 08-2002 [icn2002-hundessa.pdf]
3. Lemma Hundessa, Jordi Domingo-Pascual. Reliable and fast rerouting mechanism for a protected label switched path. IEEE Global Telecommunications Conference , pg1608-1612. Taipei, Taiwan, ROC. 11-2002 [globecom 2002-hundessa.pdf]
4. Lemma Hundessa. Enhanced Fast Rerouting Mechanisms for Protected Traffic in MPLS Networks. Universitat Politecnica de Catalunya (UPC). 04-2003 [phd2003-hundessa.pdf]

Jimenez Castells , Marta

1. M. Jiménez, J.M. Llabería, A. Fernández y E. Morancho. A Unified Transformation Technique for Multilevel Tiling. Workshop on Interaction between Compilers and Computer Architectures. San José, California. 02-1996 [interact1996-marta.ps]
   • Conjuntament amb High Performance Computer Architecture
2. M. Jiménez, J.M. Llabería, A. Fernández y E. Morancho. A Unified Transformation Technique for Multilevel Blocking. Second International Euro-Par Conference, pg402-405. Lyon,Francia. 08-1996 [euro-par1996-marta.ps]
   • Tambe publicat a: Lecture Notes in Computer Science, 1123. Springer-Verlag.
3. M. Jiménez, J.M. Llabería y A. Fernández. Performance Evaluation of Tiling for the Register Level. High Performance Computer Architecture - 4, pg254-265. Las Vegas, Nevada, USA. 01-1998 [hpca1998-marta.ps]
4. M. Jiménez, J.M. Llabería y A. Fernández. Loop Bounds Computation for Multilevel Tiling. Euromicro Workshop on Parallel and Distributed Processing, pg445-452. Madrid, España. 01-1998 [pdp1998-marta.ps]
5. M. Jiménez, J.M. Llabería, A. Fernández y E. Morancho. A General Algorithm for Tiling the Register Level. International Conference on Supercomputing 98, pg133-140. Melbourne, Australia. 07-1998 [ics1998-marta.ps]
6. M. Jimenez, J.M. Llaberia, A: Fernandez. Performance Evaluation of Tiling for the Register Level. IX Jornadas de Paralelismo, pg127-137. . 9-1998
7. Marta Jimenez Castells. Multilevel Tiling for Non-Rectangular Iteration Spaces. Universitat Politècnica de Catalunya. 05-1999 [phd1999-marta.ps]
8. M. Jiménez, J.M. Llabería y A. Fernández. On the Performance of Hand vs. Automatically Optimized Numerical Code. High Performance Computer Architecture-6, pg183-194. Toulouse, Francia. 01-2000 [hpca2000-marta.ps]
9. M. Jiménez, J.M. Llabería y A. Fernández. Register Tiling in Non-Rectangular Iteration Spaces. ACM Transactions on Programming Languages and Systems, 4, pg409-453. ACM. 07-2002 [toplas2002-marta.pdf]
10. M. Jiménez, J.M. Llabería and A. Fernández. A Cost-Effective Implementation of Multilevel Tiling. IEEE Transactions on Parallel and Distributed Systems, 10, pg1006-1020. IEEE Computer Society. 10-2003 [tpds2003-marta.ps]

Juan , Toni

1. Toni Juan, Dolors Royo and Juan J. Navarro. Dynamic Cache Splitting.. International Conference of the Chilean Computer Science Society, pg253-262. Arica, Chile. 11-1995 [icccss1995-antonioj.pdf]
2. Toni Juan, Tomás Lang and Juan J. Navarro. The Difference-bit Cache. Symposium on Computer Architecture, pg114-120. Philadelphia, USA. 05-1996 [isca1996-antonioj.gz]
3. Toni Juan, Tomás Lang and Juan J. Navarro. Reducing TLB Power Requierements. Symposium on Low Power Electronics and Design, pg196-201. Monterrey, California. 01-1997 [islpd1997-antonioj.pdf]
4. Toni Juan, Juan J. Navarro and Olivier Temam. Data Caches for Superscalar Processors. International Conference on Supercomputing, pg60-67. Vienna. 07-1997
5. Toni Juan. Technology-Conscious Cache Design. Universitat Politècnica de Catalunya (UPC). 04-1998 [phd1998-antonioj.gz]
6. Toni Juan, Sanji Sanjeevan and J. J. Navarro. Dynamic History-lenght Fitting: a Third Level of Adaptivity for Branch Prediction. 25th Annual International Symposium on Computer Architecture, pg155-166. . 7-1998
7. A. Farcy, O. Temam, R. Espasa and T. Juan. Data Flow Analysis of Branch Misspredictions and its Application to Early Resolution of Branch Outcomes. 31st International Symposium on Microarchitecture, pg59-68. . 11-1998

Larrazabal Serrano, German

1. Germán Larrazabal and José M. Cela. Parallel Algebraic Preconditioner for the Schur Complement System. International Parallel and Distributed Processing Symposium, pg. . 4-2001
2. German Larrazabal Serrano. Técnicas Algebraicas de Precondicionamiento para la Resolución de Sistemas Lineales. Universitat Politècnica de Catalunya. 5-2002

Lepe Aldama, Ivan

1. O. I. Lepe, J. García. A Performance Model of a PC Based IP Software Router. Specialist Seminar on Access Networks and Systems (ITC 14), pg. . 4-2001
2. O. I. Lepe, J. García. A Performance Model of a PC Based IP Software Router. International Conference on Comunications (ICC\'2002), pg. . 5-2002
3. O. I. Lepe, J. García. I/O bus usage control in PC-based software routers. Networking, pg. . 10-2002
4. Ivan Lepe Aldama. Modeling TCP/IP Software Implementation Performance and its applications for Software Routers. Universitat Politècnica de Catalunya. 11-2002

López , David

1. David López, Mateo Valero, Josep Llosa and Eduard Ayguadé. Increasing Memory Bandwidth with Wide Buses: Compiler, Hardware and Performance Trade-offs . International Conference on Supercomputing , pg12-19. Vienna, Austria. 7-1997 [ics1997-david.ps]
2. David López, Josep Llosa, Mateo Valero and Eduard Ayguadé. Resource Widening versus Replication: Limits and Performance-Cost Trade-off. International Conference on Supercomputing, pg441-448. Melbourne, Australia. 7-1998 [ics1998-david.ps]
3. David Lopez, Josep Llosa, Mateo Valero and Eduard Ayguade . Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. IX Jornadas de Paralelismo, pg243-250. . 9-1998
4. David López, Josep Llosa, Mateo Valero and Eduard Ayguadé. Widening Resources: A Cost-Efective Technique for Aggressive ILP Architectures . 31st Annual ACM/IEEE International Symposium on Microarchitecture , pg237-246. Dallas, USA. 12-1998 [micro1998-david.pdf]
5. David López. Recursos anchos: una técnica de bajo coste para explotar paralelismo agresivo en códigos numéricos. UPC. 12-1998
6. David López, Josep Llosa, Eduard Ayguadé and Mateo Valero. Impact on Performance of Fused Multiply-Add Units in Aggressive VLIW Architectures. International Conference on Parallel Processing , pg22-29. Aizu-Wakamatsu, Japan. 9-1999 [icpp1999-david.pdf]
7. David López, Josep Llosa, Mateo Valero and Eduard Ayguadé. Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures. IEEE Transactions on Computers, no. 10, vol. 50, pg1033-1051. IEEE. 10-2001 [tc2001-david.pdf]

Mangues Bafalluy, Josep

1. Josep Mangues-Bafalluy, Jordi Domingo-Pascual. Active Cell Discard Mechanism in ATM Networks. Elekrtosviaz Journal (in russian), 7, pg31-33. . 7-1998
2. Josep Mangues-Bafalluy, Jordi Domingo-Pascual. Compound VC Mechanism for Native Multicast in ATM Networks. 2nd International Conference on ATM (ICATM\'99), pg115-124. . 6-1999
3. Xavier Martínez-Álvarez, Josep Mangues-Bafalluy, Jordi Domingo-Pascual, Josep Solé-Pareta. Redes Virtuales ATM basadas en LANE/MPOA. Evaluación de un entorno real. Telecom I+D, pg. . 11-1999
4. Josep Mangues-Bafalluy, Jordi Domingo-Pascual. Analysis of the requirements for ATM Multicasting based on per-PDU ID Assigment. Networking 2000, pg23-35. . 5-2000
   • Tambe publicat a: Lecture Notes on Computer Science, 1815. Springer-Verlag.
5. Josep Mangues-Bafalluy, Jordi Domingo-Pascual. Performance Issues of ATM Multicasting based on per-PDU ID Assignment. International Conference on Communications (ICC2000), pg1733-1737. . 6-2000
6. Josep Mangues-Bafalluy, Jordi Domingo-Pascual. Multicast Forwarding over ATM: Native Approaches. IEEE Communications Surveys. The Electronic Magazine of Original Peer-Reviewed Survey Articles, vol. 3, no. 3, pg. . 10-2000
7. Josep Mangues Bafalluy, Jordi Domingo-Pascual, Carol Giné Sadó, Guifré Esquerrà Rovira. Evaluación de EF PHB en una red de Servicios Diferenciados. XI Jornadas TELECOM I+D 2001, pg. . 11-2001
8. Josep Mangues-Bafalluy, Jordi Domingo-Pascual. TheCompound VC switch. A non-VC merge ATM multicast switch. International Conference on Communications (ICC2002), pg2111-2115. . 5-2002
9. Josep Mangues Bafalluy. Provisioning of Multipoint-to-Multipoint Communications in an MPLS ATM Label Switch Router. Universitat Politècnica de Catalunya. 4-2003

Marcuello Pascual , Pedro

1. Pedro Marcuello y Antonio Gonzalez. Exploiting Multithreading Through Control and Data Dependence Speculation. Poster Session. Bangalore (India). 12-1997 [hipc1997-pedrox.marcuello.ps]
   • Conjuntament amb 4th Int. Symp. on High Performance Computing
2. Pedro Marcuello y Antonio Gonzalez. Control and Data Dependence Speculation in Multithreaded Processors. Multithreaded Execution, Architectures and Compilation Techniques. Las Vegas, NV (Estats Units). 1-1998 [mteac1998-pedrox.marcuello.ps]
   • Conjuntament amb 4th Int. Symp. on High Performance Computer Architecture
3. Pedro Marcuello, Antonio Gonzalez y Jordi Tubella. Speculative Multithreaded Processors. 12th Int. Conference on Supercomputing, pg77-84. Melbourne (Australia). 7-1998 [ics1998-pedrox.marcuello.ps]
4. Pedro Marcuello y Antonio Gonzalez. Data Speculative Multithreaded Architecture. Workshop on Digital System Design: Architectures, Methods and Tools. Vasteras (Suecia). 8-1998 [dsd1998-pedrox.marcuello.ps]
   • Conjuntament amb Euromicro
5. Pedro Marcuello y Antonio Gonzalez. Exploiting Speculative Thread-Level Parallelism on a SMT Processor. 7th Int. Symp. on High-Performance Computing and Networking, pg754-763. Amsterdam (Holanda). 4-1999 [hpcn1999-pedrox.marcuello.ps]
6. Pedro Marcuello y Antonio Gonzalez. Clustered Speculative Multithreaded Processors. 13th Int. Conference on Supercomputing, pg365-372. Rhodes (Grecia). 6-1999 [ics1999-pedrox.marcuello.ps]
7. Pedro Marcuello, Jordi Tubella and Antonio Gonzalez. The Increment Predictor for Speculative Multithreaded Processors. IX Jornadas de Paralelismo, pg113-118. . 9-1999
8. Pedro Marcuello, Jordi Tubella y Antonio Gonzalez. Value Prediction for Speculative Multithreaded Architectures. 32nd Int. Symp. on Microarchitecture, pg230-236. Haifa (Israel). 11-1999 [micro1999-pedrox.marcuello.pdf]
9. Pedro Marcuello y Antonio Gonzalez. A Quantitative Assessment of Thread-level Speculation Techniques. 15th Int. Parallel and Distributed Processing Symposium, pg595-601. Cancun (Mexico). 5-2000 [ipdps2000-pedrox.marcuello.pdf]
10. Pedro Marcuello y Antonio Gonzalez. Thread-Spawning Schemes for Speculative Multithreading. 8th Int. Symp. on High Performance Computer Architecture, pg48-57. Cambridge, MA (Estats Units). 2-2002 [hpca2002-pedrox.marcuello.pdf]
11. Pedro Marcuello Pascual. Speculative Multithreaded Processors. Universitat Politecnica de Catalunya. 7-2003 [phd2003-pedrox.marcuello.zip]
12. Pedro Marcuello, Jordi Tubella y Antonio Gonzalez. Thread Partitioning and Value Prediction for Exploiting Speculative Thread Level Parallelism. IEEE Transaction on Computers, 53-2, pg114-125. IEEE Computer Society. 2-2004 [ieeetc2004-pedrox.marcuello.pdf]

Marquès i Puig , Joan Manel

1. Marques J.M., Navarro L.. WWG: A Wide-area Infrastructure for Groups. E-CSCL 2001. Maastrich, Belgium. 2-2001
2. Marquès J.M., Navarro L.. WWG: a Wide-Area Infrastructure for Group Work. 10th IEEE International Workshops on Enabling Technologies: Infrastructures for Collaborative Enterprises, pg342-347. Cambridge, Massachusetts,USA. 06-2001 [wet ice2001-marques.pdf]
3. Marquès J.M., Navarro L.. WWG: a Wide-Area Infrastructure to support groups. roceedigns of 2001 International ACM SIGGROUP Conference on Supporting Group Work, pg179-187. Boulder, Colorado, EUA. 09-2001 [group2001-marques.pdf]
4. Marquès J.M., Navarro L., Daradoumis, A. . WWG: a Distributed Infrastructure for Learning in Groups. Frontiers in Education Conference, pg. Reno, Nevada, EUA. 10-2001 [fie2001-marques.pdf]
5. Joan Manuel Marquès i Puig. LaCOLLA: una infraestructura autònoma i autoorganitzada per facilitar la col·laboració.. UPC. 12-2004 [phd2004-marques.pdf]

Marti Escalé, Ramon

1. Ramon Marti Escalé. Aplicacions Distribuides per Manipular Documents. Universitat Politècnica de Catalunya. 11-1998

Martorell , Xavier

1. Xavier Martorell, Jesús Labarta, Nacho Navarro, Eduard Ayguadé. Library Implementation of the Nano-Threads Programming Model. Second International Euro-Par Conference, pg644-649. Lyon, France. 8-1996 [europar1996-xavim.ps]
   • Tambe publicat a: Lecture Notes in Computer Science, 1124. Springer-Verlag.
2. Xavier Martorell, Jesús Labarta, Nacho Navarro, Eduard Ayguadé. Analysis of Several Scheduling Algorithms under the Nano-Threads Programming Model. International Parallel Processing Symposium, pg281-287. Ginebra, Suiza. 4-1997 [ipps1997-xavim.ps]
3. Eleftherios D. Polychronopoulos, Xavier Martorell, Dimitrios S. Nikolopoulos, Jesús Labarta, Theodore S. Papatheodorou, Nacho Navarro. Kernel-Level Scheduling for the Nano-Threads Programming Model. 12th ACM International Conference on Supercomputing , pg13-17. Melbourne, Australia. 7-1998 [ics1998-xavim.ps]
4. Xavier Martorell, Eduard Ayguadé, Nacho Navarro, Julita Corbalán, Marc Gonzàlez and Jesús Labarta. Thread Fork/Join Techniques for Multi-level Parallelism Exploitation in NUMA Multiprocessors. 13th ACM International Conference on Supercomputing , pg20-25. Rhodes, Greece. 6-1999 [ics1999-xavim.ps]
5. Xavier Martorell. Dynamic Scheduling of Parallel Applications on Shared-Memory Multiprocessors. UPC. 7-1999 [phd1999-xavim.ps]
6. X. Martorell, E. Ayguade, J. Labarta and J.I. Navarro. Improving the Performance of Multiprogrammed Workloads in Origin2000 Systems. 5th European Cray/SGI MPP Workshop . . 9-1999
7. Eduard Ayguadé, Xavier Martorell, Jesús Labarta, Marc Gonzàlez, Nacho Navarro. Exploiting Multiple Levels of Parallelism in OpenMP: A Case Study. 29th IEEE Annual International Conference on Parallel Processing , pg21-24. Aizu-Wakamatsu, Japan. 9-1999 [icpp1999-xavim.ps]
8. Xavier Martorell, Julita Corbalán, Dimitris Nikolopoulos, Nacho Navarro, Elefterios Polychronopoulos, Theodore Papatheodorou. A Tool to Schedule Parallel Applications on Multiprocessors: The NANOS CPU Manager. Workshop on Job Scheduling Strategies for Parallel Processing, pg55-69. Cancún, México. 5-2000 [ipdps2000-xavim.pdf]

Masip Bruin , Xavier

1. Xavi Masip Bruin, Sergi Sànchez López, Josep Solé Pareta, Jordi Domingo Pascual. An Alternative Path Fast Rerouting in MPLS. Fifteenth International Symposium on Computer and Information Sciences, pg9. Estambul, Turquia. 10-2000 [iscis2000-xmasip.pdf]
2. Xavi Masip Bruin, Raul Muñoz, Sergi Sànchez López, Josep Solé Pareta, Jordi Domingo Pascual, Gabreil Junyent. Mecanismo de Encaminamiento Dinámico en Redes ASON. XII Jornadas Telecom I+D, pg14. Barcelona, Madrid. 11-2002 [telecom2002-xmasip.pdf]
3. Xavi Masip Bruin, Raul Muñoz, Sergi Sànchez López, Josep Solé Pareta, Jordi Domingo Pascual, Gabriel Junyent. An Adaptive Routing Mechanism for Reducing the Routing Inaccuracy Effects in an ASON. Seventh IFIP Working Conference on Optical Network Design & Modelling, pg19. Budapest, Hungria. 02-2003 [ondm2003-xmasip.pdf]
4. Xavi Masip Bruin, Sergi Sànchez Lópz, Josep Solé Pareta. QoS Routing Algorithms under Inaccurate Routing Information for Bandwidth Constrained Applications. IEEE International Conference on Communications, pg6. Anchorage, Alaska, USA. 05-2003 [icc2003-xmasip.pdf]
5. Josep Solé Pareta, Xavier Masip Bruin, Sergio Sánchez López, salvatore Spadaro, Davide Careglio. Some Open Issues in the Optical Networks Control Plane. 5th International Conference on Transparent Optical Networks, pg. Varsòvia, Polònia. 06-2003 [icton2003-xmasip.pdf]
6. Xavier Masip Bruin. Mechanisms to Reduce Routing Information Inaccuracy Effects: Application to MPLS and WDM Networks. Universitat Politècnica de Catalunya. 10-2003
7. P.Van Mieghem, F.A.Kuipers, T.Korkmaz, M.Krunz, M.Curado, E.Monteiro, X.Masip, J.Solé, S.Sànchez. Quality of Service Routing. Lecture Notes in Computer Science, 2856, pg37. Springer. 10-2003 [lncs2003-xmasip.pdf]
8. Xavi Masip, Bruin, Sergi Sànchez López, Josep Solé Pareta, Jordi Domingo Pascual, Didier Colle. Routing and wavelength Assignment under Inaccurate Routing Information in Networks with Sparse and Limited Wavelngth Conversion . IEEE Global Telecommunications Conference, pg5. San Francisco, USA. 12-2003 [globecom2003-xmasip.pdf]
9. Xavier Masip bruin, Sergi Sànchez López, , Josep solé Pareta, Jordi Domingo Pascual, Eva Marín Tordera. Hierarchical Routing with QoS Constraints in Optical Transport Networks. The Third IFIP-TC6 Networking Conference, pg12. Atenes, Grècia. 5-2004 [networking2004-xmasip.pdf]
   • Tambe publicat a: Lecture Notes in Computer Science, . Springer.

Morancho Llena , Enric

1. Enric Morancho, Jose Maria Llaberia, Angel Olive, Marta Jiménez. Reducing the Influence of Memory Access Instructions on Stall Cycles. VIII Jornadas de Paralelismo, pg161-170. Cacers. 9-1997 [jp1997-enricm.pdf]
2. Enric Morancho, Jose Maria Llaberia, Angel Olivé and Marta Jiménez. One-Cycle Zero-Offset Loads. Europan Parallel and Distributed Systmes, pg87-93. Viena. 7-1998 [pds1998-enricm.ps]
3. Enric Morancho, Jose M. Llaberia and Angel Olive. Split Last-address Predictor. IX Jornadas de Paralelismo, pg275-282. . 9-1998
4. Enric Morancho, Jose Maria Llaberia and Àngel Olivé. Split Last-Address Predictor. Parallel Architecture and Compilation Techniques, pg230-239. Paris. 10-1998 [pact1998-enricm.ps]
5. Enric Morancho, Jose M. Llaberia and Angel Olive. Two-level Address Storage and Address Prediction. X Jorndas de Paralelismo, pg29-37. . 9-1999
6. Enric Morancho, Jose Maria Llaberia and Angel Olivé. Looking at History to Filter Allocations in Precition Tables. Parallel Architectures and Compilation Techniques, pg314-319. New Port Beach, California, EEUU. 10-1999 [19991999-enricm.ps]
7. Enric Morancho, Jose Maria Llaberia and Angel Olivé. Two-Level Address Storage and Address Prediction. Euro-Par, pg960-964. Munich. 8-2000 [euro-par2000-enricm.ps]
   • Tambe publicat a: Lecture Notes on Computer Science , 1900. Springer.
8. Enric Morancho, Jose Maria Llaberia and Angel Olivé. Recovery Mechanism for Latency Misprediction. Parallel Architecture and Compilation Techniques, pg118-128. Barcelona. 9-2001 [pact2001-enricm.ps]
9. Enric Morancho Llena. Address Prediction and Recovery Mechanisms. UPC. 7-2002 [phd2002-enricm.pdf]

Ortega , Daniel

1. Daniel Ortega, Ivan Martel, Venkata Krishnan, Eduard Ayguade and Mateo Valero. A Characterization of Parallel SPECint Programs in Simultaneous Multithreading Architectures. X Jornadas de Paralelismo, pg119-124. . 9-1999
2. Daniel Ortega, Ivan Martel, Venkata Khrishnan, Eduard Ayguade and Mateo Valero. Quantifying the Benefits of SPECint Distant Parallelism in Simultaneous Multithreading Architectures. International Conference on Parallel Architectures and Compilation Techniques (PACT’99), pg117-124. . 10-1999 [pact1999-dortega.ps]
3. Daniel Ortega, Mateo Valero and Eduard Ayguadé. A Novel Renaming Mechanism that Boosts Software Prefetching. International Conference on SuperComputing 2001, pg501-510. Sorrento, Italia. 06-2001 [ics2001-dortega.pdf]
4. Daniel Ortega, Eduard Ayguadé, Jean-Loup Baer and Mateo Valero. Cost-Effective Compiler Directed Memory Prefetching and Bypassing. Parallel Architectures and Compilation Techniques 2002, pg189-198. Charlottesville, Virgina, USA. 9-2002 [pact2002-dortega.pdf]
5. Daniel Ortega, Mateo Valero and Eduard Ayguadé. Dynamic Memory Instruction Bypassing. International Conference on Supercomputing , pg316 - 325. San Francisco, CA, USA. 6-2003 [ics2003-dortega.pdf]
6. Daniel Ortega. Memory Instruction Bypassing. Universidad Politécnica de Cataluña. 7-2003 [phd2003-dortega.pdf]

Peña Basurto, Marco Antonio

1. E.Pastor, J.Cortadella and M.A. Peña. Structural Methods to Improve the Symbolic Analysis of Petri Nets. 20th International Conference on Application and Theory of Petri Nets, pg26-45. . 6-1999
   • Tambe publicat a: Lecture Notes in Computer Science, 1639. .
2. Marco A. Peña, Jordi Cortadella, Alex Kondratyev and Enric Pastor. Formal Verification of Safety Properties in Timed Circuits. Sixth International Symposium on Advanced Research in Asynchronous Circuits and Systems, pg2-11. . 4-2000
3. Marco Antonio Peña Basurto. Relative Timing Based Verification of Concurrent Systems. Universitat Politècnica de Catalunya. 4-2003

Ramirez , Alex

1. Alex Ramirez, Josep Ll. Larriba-Pey, Carlos Navarro,Josep Torrellas and Mateo Valero. Software Trace Cache. 13th ACM-SIGARCH International Conference on Supercomputing, pg119-126. Rhodes (Greece). 6-1999 [ics1999-aramirez.ps]
2. Alex Ramirez, Josep Ll. Larriba-Pey, Carlos Navarro, Xavi Serrano,Josep Torrellas and Mateo Valero. Optimization of Instruction Fetch for Decision Support Workloads. Intl. Conference on Parallel Processing, pg238-245. Aizu-Wakamatsu, Fukushima (Japan). 9-1999 [icpp1999-aramirez.ps]
3. Alex Ramirez, Josep Ll. Larriba-Pey, and Mateo Valero. Trace cache redundancy: Red & blue traces. 6th Intl. Conference on High Performance Computer Architecture, pg325-333. Tolouse (France). 1-2000 [hpca2000-aramirez.ps]
4. Alex Ramirez, Josep L. Larriba-Pey, and Mateo Valero. A stream processor front-end. IEEE TCCA Newsletter, , pg. IEEE Computer Society. 6-2000 [tcca2000-aramirez.ps]
5. Carlos Navarro, Alex Ramirez, Josep Ll. Larriba-Pey and Mateo Valero. On the performance of fetch engines running DSS workloads. Intl. EuroPar Conference, pg940-949. Munich (Germany). 8-2000
   • Tambe publicat a: Lecture Notes in Computer Science, 1900. Springer-Verlag.
6. Alex Ramirez, Josep L. Larriba-Pey, and Mateo Valero. The effect of code reordering on branch prediction. Intl. Conference on Parallel Architectures and Compilation Techniques, pg189-198. Philadelphia (Pensilvania). 10-2000 [pact2000-aramirez.ps]
7. Alex Ramirez, Luiz Barroso, Kourosh Gharachorloo, Robert Cohn, Josep L. Larriba-Pey, Geoffrey Lawney, and Mateo Valero. Code layout optimizations for transaction processing workloads. 28th Annual Intl. Symposium on Computer Architecture, pg155-164. Goteborg (Sweden). 7-2001 [isca2001-aramirez.ps]
8. Alex Ramirez, Josep L. Larriba-Pey, and Mateo Valero. Branch prediction using profile data. Intl. EuroPar Conference, pg386-393. Manchester (UK). 8-2001 [europar2001-aramirez.ps]
   • Tambe publicat a: Lecture Notes in Computer Science, 2150. Springer-Verlag.
9. Alex Ramirez, Josep L. Larriba-Pey, and Mateo Valero. Instruction fetch architectures and code layout optimizations. Proceedings of the IEEE: Special issue on Microprocessor architecture and compiler technology, 89(11), pg. IEEE Computer Society. 11-2001 [ieee2001-aramirez.ps]
10. M. Eng, H. Wang, P. Wang, A. Ramirez, J. Fung, and J. Shen. Mesocode: Optimizations for Improving Fetch Bandwidth of Itanium Processors. Workshop on Complexity-Effective Design. Anchorage (Alaska). 5-2002 [wced2002-aramirez.pdf]
    • Conjuntament amb 29th Annual Intl. Symposium on Computer Architecture
11. Alex Ramirez. High-performance Instruction Fetch Using Software and Hardware Co-design. Universitat Politecnica de Catalunya. 6-2002 [phd2002-aramirez.pdf]
    • Publicada per: TDC@T (ISBN 84-699-9296-1)
12. P. M. W. Knijnenburg, A. Ramirez, F. Latorre, J. Larriba, and M. Valero. Branch Classification to Control Instruction Fetch in Simultaneous Multithreaded Architectures. 2002 International Workshop on Innovative Architecture, pg67-76. Hawai. 8-2002
13. Alex Ramirez, Josep Larriba-Pey, Josep Torrellas, Mateo Valero. Software Trace Cache for Commercial Applications. Intl. Journal on Parallel Programming, 30(5), pg. Kluwer Academic Publishers. 10-2002 [ijpp2002-aramirez.ps]
14. Alex Ramirez, Oliverio Santana, Josep Larriba-Pey, Mateo Valero. Fetching Instruction Streams. 35th Intl. Symposium on Microarchitecture, pg371-382. Istambul, Turkey. 11-2002 [micro2002-aramirez.ps]
15. Alex Ramirez, Josep Larriba-Pey, Mateo Valero. Software Trace Cache. IEEE Transactions on Computers, , pg. IEEE Computer Society. 12-2004 [toc2004-aramirez.ps ]

Rodriguez Mulà, Gerard

1. Leandro Navarro y Gerard Rodríguez. Leandro Navarro y Gerard Rodríguez. Simposio Español de Informática Distribuida, pg. . 2-1999
2. Gerard Rodriguez Mulà. Federation Mechanisms for Large Scale Cooperative Systems. Universitat Politècnica de Catalunya. 3-1999

Royo , Dolors

1. Dolors Royo, Miguel Valero-García, Antonio González and Carme Marí. (. A Methodology for User-Oriented Scalability Analysis. . In IEEE International Conference on Application Specific Systems, Architectures, and Processors , pg304-315. Zurich. 7-1997
2. Dolors Royo, Miguel Valero-García and Antonio González. (PDP’98), pp. 463-469, January 1998. . A Jacobi-based Algorithm for Computing Symmetric Eigenvalues and Eigenvectors in a Two-Dimensional Mesh. . Sixth Euromicro Workshop on Parallel and Distributing Processing . Madrid. 1-1998
   • Conjuntament amb Sixth Euromicro Workshop on Parallel and Distributing Processing
3. Dolors Royo, Antonio González and Miguel Valero-García.. Jacobi Orderings for Multi-Port Hypercubes. . In 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, pg88-97. Florida. 3-1998 [ipps/spdp1998-dolors.pdf]
4. Dolors Royo, Antonio González and Miguel Valero-García. Low Communication Overhead Jacobi Algorithms for Eigenvalue Computation on Hypercubes. Journal of Supercomputing, 2, pg171-194. . 1-1999 [js1999-dolors.pdf]
5. Dolors Royo. “Una Contribució al Càlcul de Valors i Vectors Propis i a l’Anàlisi de l’Escalabilitat“ . Universidad Politécnica de Cataluña. 1-1999 [phd1999-dolors.pdf]
6. Dolors Royo, Miguel Valero-Garcia and Antonio Gonzalez. Jacobi Ordering for Multiple-port Hypercubes. Workshop on Frontiers of Parallel Numerical Computations and Applications (Frontiers\\\'99), pg1-10. . 2-1999
   • Tambe publicat a: Parallel Numerical Computation with Applications, . Kluwer Academic Publishers.
7. Dolors Royo, Miguel Valero-García and Antonio González. . Implementing the One-Sided Jacobi Method on a 2d/3d Mesh Multicomputer. . Parallel Computing, 9, pg1253-1271. . 8-2001 [parco2001-dolors.pdf]

Sanchez del Castillo, Ricardo Xavier

1. Ricardo Xavier Sanchez del Castillo. Secure Delegation of Computing and Data in Unsafe Distributed Systems. Universidad Politécnica de Cataluña. 2-1999

Sanchez Lopez , Sergio

1. Sergio Sánchez-López, Xavier Masip-Bruin, Josep Solé-Pareta, Jordi Domingo-Pascual. A Solution for Integrating MPLS over ATM. : Fifteenth International Symposium on Computer and Information Sciences, pg304-312. Estambul, Turquía. 10-2000 [iscis2000-sergio.pdf]
2. Sergio Sánchez-López, Xavier Masip-Bruin, Jordi Domingo-Pascual, Josep Solé-Pareta, Juanjo López-Mellado. A Path Establishment Approach in an MPLS-ATM Integrated Environment. IEEE Global Communications , pg2676-2681. San Antonio, USA. 11-2001 [globecom2001-sergio.pdf]
3. Sergio Sánchez-López, Xavier Masip-Bruin, Josep Solé-Pareta, Jordi Domingo-Pascual. Providing QoS in MPLS-ATM Integrated Environments. LECTURE NOTES IN COMPUTER SCIENCE, 2511 , pg215-224. Springer Verlag. 10-2002 [ lncs2002-sergio.pdf]
4. Sergio Sánchez-López, Xavier Masip-Bruin, Josep Solé-Pareta, Jordi Domingo-Pascual. A routing information exchange protocol for ASON. Powerful Networks for Profitable Services, Eurescom Summit 2002, pg109-116. Heidelberg, Alemania. 10-2002 [ eurescom2002-sergio.pdf]
5. Sergio Sánchez-López, Xavier Masip-Bruin, Josep Solé-Pareta, Jordi Domingo-Pascual. Providing QoS in MPLS_ATM Integrated Environment. Third COST 263 International Workshop on Quality of Future Internet Services . Zurich, Switzerland. 10-2002 [qofis2002-sergio.pdf]
6. J. Solé-Pareta, D. Careglio, X. Masip-Bruin, S. Sanchez-López and S. Spadaro. Some Open Issues in the Definition of a Control Plane for Optical Networks. IEEE 5th International Conference on Transparent Optical Networks, pg. Warsaw, Poland. 06-2003 [icton2003-sergio.pdf]
7. De Maesschalck, D. Colle, B. Puype, Q. Yan, M. Pickavet, P. Demeester, S.Sánchez-López, X.Masip-Bruin, J. Solé-Pareta, et al. Circuit/Wavelength Switching and Routing. 7th. International Conference on Telecommunications, pg. Zagreb, Croatia. 06-2003 [contel2003-sergio.pdf]
8. Sergio Sanchez Lopez. Interconnection of IP/MPLS Networks Through ATM and Optical Backbones Using PNNI Protocols. Universitat Politècnica de Catalunya. 10-2003 [phd2003-sergio.pdf]
9. S. Sánchez-López, J. Solé-Pareta, J. Comellas, J. Soldatos, G. Kylafas, M. Jaeger. PNNI Based Control Plane for Automatic Switched Optical Networks. IEEE Journal of Lightwave Technology, Special Issue on Optical Networks, vol. 21, nº11, pg2673-2682. IEEE/OSA publications. 11-2003 [jlt2003-sergio.pdf]
10. J. Soldatos, G. Pikramenos, G. E. Kylafas, B. Lianos, S. Sánchez-López, J. Solé-Pareta. Implementation PNNI Signalling in the Optical Control Plane. Scientific and Engineering Academy and Society Transactions on Circuits, 2, pg171-177. wseas. 02-2004 [wseas2004-sergio.pdf]

Sosa Sosa, Victor

1. Leandro Navarro, Victor J. Sosa y Oscar Ardaiz. Document Distribution to Internet Digital Libraries. Simposio Español de Informática Distribuida, pg. . 2-1999
2. Victor J. Sosa, Leandro Navarro. Proxycizer2ns: A Suitable Combination for Web Caching and Replication Study. Simposio Español de Informática Distribuida, pg. . 9-2000
3. Victor Sosa, Leandro Navarro. Influence of the Document Validation/Replication Methods on Cooperative Web Caching Architectures. Communication Networks and Distributed Systems Modeling and Simulation Conference, pg. . 1-2002
4. Victor Sosa, Leandro Navarro. A New Environment for Web Caching and Replication Study. Jornadas Chilenas de Computación, pg. . 6-2002
5. Victor Sosa Sosa. Arquitectura para la Distribución de Documentos en un Sistema Distribuido a Gran Escala. Universitat Politècnica de Catalunya. 11-2002

Sánchez Navarro , Jesus

1. Jesús Sánchez, Antonio González and Mateo Valero. Static Locality Analysis for Cache Management. 1997 International Conference on Parallel Architectures and Compilation Techniques , pg261-271. . 11-1997
2. Jesús Sánchez and Antonio González. Cache Sensitive Modulo Scheduling. 30th Annual International Symposium on Microarchitecture , pg338-348. . 12-1997
3. Jesus Sanchez and Antonio Gonzalez. Data Locality Analysis of the SPECfp95. Workshop on Performance Analysis and its Impact on Design. . 6-1998
   • Conjuntament amb International Symposium on Computer Architecture
4. Jesús Sánchez and Antonio González. Fast, Flexible and Accurate Data Locality Analysis. 1998 International Conference on Parallel Architectures and Compilation Techniques, pg124-129. . 10-1998
5. Jesús Sánchez and Antonio González. Caching Data According to their Locality. 12th Int. Conf. on Control Systems and Computer Science , pg139-144. . 5-1999
6. Jesús Sánchez and Antonio González. A Locality Sensitive Multi-Module Cache with Explicit Management. International Conference on Supercomputing , pg51-59. . 6-1999
7. Jesús Sánchez and Antonio González. Software Data Prefetching for Software Pipelined Loops. Journal of Parallel and Distributed Computing, vol. 58, no. 2, pg236-259. . 8-1999
8. Jesús Sánchez and Antonio González. Analyzing Data Locality in Numeric Applications. IEEE Micro, vol. 20, no. 4, pg58-66. . 7-2000
9. Jesús Sánchez and Antonio González. The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. 29th. Int. Conf. on Parallel Processing , pg555-562. . 8-2000
10. Jesús Sánchez and Antonio González. Instruction Scheduling for VLIW Architectures. 13th International Symposium on System Synthesis , pg41-46. . 9-2000
11. Jesús Sánchez and Antonio González. Modulo Scheduling for a Fully-Distributed Clustered VLIW Architecture. 33th Annual IEEE/ACM International Symposium on Microarchitecture, pg124-133. . 12-2000
12. Jesus Sánchez Navarro. Smart Memory Management through Locality Analysis. Universitat Politècnica de Catalunya . 11-2001
13. Jesús Sánchez, Enric Gibert and Antonio González. Compilation Techniques for a Word-Interleaved Cache Clustered VLIW Processor. International Conference on Parallel Processing, pg. . 1-2003

Vila Sallent, Joan

1. Joan Vila Sallent. A Network architecture for supporting parallel computing over ATM. Universitat Politècnica de Catalunya. 11-1997

Villa Vargas , Luis A.

1. Luis A. Villa, Roger Espasa and Mateo Valero. Effective Usage of Vector Registers in Advanced Vector Architectures. 1997 International Conference on Parallel Architectures and Compilation Techniques , pg250-260. . 11-1997
2. Luis A. Villa, Roger Espasa and Mateo Valero. Effective Usage of Vector Registers in Decoupled Vector Architectures. Sixth Euromicro Workshop on Parallel and Distributing Processing , pg495-501. . 1-1998
3. Luis A. Villa, Roger Espasa and Mateo Valero. Rendimiento de una Cache Escalar en una Arquitectura Vectorial Fuera de Orden. 8th International Conference of Electronics Communications and Computers, pg230-235. . 2-1998
4. Luis A. Villa, Roger Espasa and Mateo Valero. Registers Size Influence on Vector Architectures. 3rd International Meeting on Vector and Parallel Processing , pg495-506. . 6-1998
5. Luis A. Villa, Roger Espasa and Mateo Valero. A Performance Study of Out-of-order Vector Architectures and Short Registers. International Conference on Supercomputing , pg37-44. . 7-1998
6. Luis A. Villa Vargas. Evaluación de Arquitecturas Vectoriales Avanzadas en Registros Cortos. Universidad Politécnica de Cataluña. 7-1999

Zalamea León , Javier

1. J. Zalamea, J. Llosa, E. Ayguade and M. Valero. Memory Controlled Spill Code for Software Pipelining. X Jornadas de Paralelismo, pg131-136. . 9-1999
2. J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Improved Spill Code Generation for Software Pipelined Loops. ACM SIGPLAN 2000 Conference on Programming Language Design and Implementation , pg134-144. . 6-2000 [pldi2000-jzalamea.ps]
3. J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Two-level Hierarchical Register File Organization for VLIW Processors . 33rd Annual IEEE/ACM International Symposium on Microarchitecture , pg137-146. . 12-2000 [micro2000-jzalamea.ps]
4. J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Software and Hardware Techniques to Optimize Register File Utilization in VLIW Architectures. The International Workshop on Advanced Compiler Technology for High Performance and Embedded Systems, pg. . 7-2001 [act2001-jzalamea.ps]
5. J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. MIRS: Modulo Scheduling with Integrated Register Spilling . 14th Workshop on Languages and Compilers for Parallel Computing, pg239-253. . 8-2001 [lcpc2001-jzalamea.ps]
   • Tambe publicat a: Lecture Notes in Computer Science , 2624. .
6. J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Modulo Scheduling with Integrated Register Spilling for Clustered VLIW Architectures. 34th Annual International Symposium on Microarchitecture, pg160-169. . 12-2001 [micro2001-jzalamea.pdf]
7. Javier Zalamea León. Organization and Compiler Management of Register Files. Universitat Politècnica de Catalunya. 12-2002
8. J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Hierarchical Clustered Register File Organization for VLIW Processors. 2003 International Parallel and Distributed Processing Symposium , pg. . 4-2003 [ipdps2003-jzalamea.pdf]
9. J. Zalamea, J. Llosa, E. Ayguadé and M. Valero. Register-constrained Modulo Scheduling. IEEE Transactions on Parallel and Distributed Systems, vol. 15, no. 6, pg. . 6-2004 [tpds2004-jzalamea.pdf]